Abstract: We present an implementation of a complete RLS Lattice and Normalised RLS Lattice cores for Virtex. The cores accept 24-bit fixed point inputs and produce 24-bit fixed point prediction error. Internally, the computations are based on 32bit logarithmic arithmetic. On Virtex XCV2000E-6, it takes 22% and 27% of slices respectively and performs at 45 MHz. The cores outperform (4-5 times) the standard DSP solution based on 32 bit floating point TMS320C3x/4x 50MHz processors.
Abstract:In this paper we present several implementations of the Modified A Priori Error-Feedback LSL (EF-LSL) algorithm [1] on the VIRTEX FPGA. Its computational parallelism and pipelinabilty are important advantages. Internally, the computations are based on the logarithmic number system. We compare 32-bit (SINGLE-ALU or DUAL-ALU version) and 20-bit (QUADRI-ALU versions). We show that the LNS implementation can outperform the standard DSP solutions based on 32-bit floating-point processors.
Abstract: The QR-decomposition-based least-squares lattice (QRDLSL) algorithm is one of the most attractive choices for adaptive filters applications, mainly due to its fast convergence rate and good numerical properties. In practice, the square-root-free QRD-LSL (SRF-QRD-LSL) algorithms are frequently employed, especially when fixed point digital signal processors (DSPs) are used for implementation. In this context, there are some major limitations regarding the large dynamic range of the algorithms cost functions.Consequently, hard scaling operations are required, which further reduce the precision of numerical representation and lead to performance degradation. In this paper wepropose a SRF-QRD-LSL algorithm based on a modified update of the cost functions, which offers improved numerical robustness. Simulations performed in fixed-point andlogarithmic number system (LNS) implementation support the theoretical findings.